A PLA (programmable logic array) is commonly known as flexibly providing a sum of products function of input signals. A PLA typically includes an AND-plane and an OR-plane for providing the sum of products. A DPLA (dynamic programmable logic array) also includes clock signals for controlling timing of operation of the DPLA.
FIG. 1 shows a conventional DPLA 100 using a first clock signal CLK1 for an AND-plane and a second clock signal CLK2 for an OR-plane. The AND-plane includes first and second product term lines, 102 and 104 respectively, having product terms, f1* and f2* respectively, generated thereon. Four inputs, a*, b*, c, and d* are applied on four input lines 106 as illustrated in FIG. 1. (Note that “*” herein refers to a complement of a signal as commonly known to one of ordinary skill in the art).
CLK1 is coupled to the gates of a first PMOSFET MP1 and a first NMOSFET MN1 that are coupled to high and low voltages, VDD and VSS respectively, for charging/discharging the first product term line 102 depending on a logical state of CLK1. CLK1 is also coupled to the gates of a second PMOSFET MP2 and a second NMOSFET MN2 that are coupled to VDD and VSS respectively for charging/discharging the second product term line 104 depending on the logical state of CLK1.
When CLK1 is a logical low state (i.e., “0”) during a pre-charge time, the product term lines 102 and 104 are each pre-charged to a logical high state (i.e., “1”). Because of the connections of NMOSFETs MN5, MN6, MN7, and MN8 in the AND-plane of FIG. 1, when CLK1 is a logical high state during an evaluation time, the respective logical state of each of f1* and f2* on the product term lines 102 and 104 depends on the logical states of the inputs, a*, b*, c, and d*, as follows:f1*=a×bf2*=c*×d(Note that “x” herein refers to an AND operation, and “+” herein refers to an OR operation, as commonly known to one of ordinary skill in the art.)
Further referring to FIG. 1, CLK2 is coupled to the gates of a third NMOSFET MN3, a third PMOSFET MP3, a fourth NMOSFET MN4, and a fourth PMOSFET MP4. The PMOSFETs MP3 and MP4 are coupled to VDD, and the NMOSFETs MN3 and MN4 are coupled to VSS. When CLK2 is a logical low state during a pre-charge time, a pre-output line 108 having a signal F* generated thereon is pre-charged to a logical high state. An output line 110 having a signal F generated thereon is coupled to the pre-output line 108 via an inverter 112.
Because of the connections of NMOSFETs MN9 and MN10 in the OR-plane of FIG. 1, when CLK2 is a logical high state during an evaluation time, the respective logical state of F depends on the logical states of f1* and f2* and thus of the inputs, a*, b*, c, and d*, as follows:F*=f1×f2F=f1*+f2*=(a×b)+(c*×d)Thus, the output line 110 provides an OR-function of the product terms f1* and f2*.
FIG. 2 shows a DPLA (dynamic programmable logic array) 150, and FIG. 3 shows a timing diagram during operation of the DPLA 150 of FIG. 2, as disclosed in U.S. Pat. No. 5,083,047 to Horie et al. The AND-plane of the DPLA 150 generates product terms on product term lines 1011 from inputs A, A*, B, and B* on input lines 1010. The OR-plane of the DPLA 150 generates outputs, Y1 and Y2, via output lines 1012.
Referring to FIGS. 2 and 3, the DPLA 150 includes a first clock signal Ø1 for the AND-plane and a second clock signal Ø2 for the OR-plane. A first group of PMOSFETs and NMOSFETs 152 are coupled to VDD and a ground node and receive Ø1 for charging/discharging the product term lines 1011 depending on the logical state of Ø1. A second group of PMOSFETs and NMOSFETs 154 are coupled to VDD and the ground node and receive Ø2 for charging/discharging the output lines 1012 depending on the logical state of Ø2.
The connections of NMOSFETs N1 determine a respective product term on each of the product term lines 1011 as an AND-function of a respective set of inputs. The connections of the NMOSFETs N2 determine an OR-function of a respective set of product terms for each of the output lines 1012.
Referring to FIGS. 2 and 3, when Ø1 is a logical high state during an AND-plane pre-charge time, each of the product term lines 1011 is pre-charged to a logical high state. When Ø2 is a logical high state during an OR-plane pre-charge time, each of the output lines 1012 is pre-charged to a logical high state. When Ø1 turns to a logical low state for an AND-plane evaluation time, the respective logical state for each of the product term lines 1011 becomes valid after a propagation delay tp from when Ø1 turns to the logical low state.
Further referring to FIG. 3, Ø2 for the OR-plane is delayed from Ø1 for the AND-plane by Δt to ensure that the product terms are valid before generating the OR-function of such product terms on the output lines 1012. Thus, Δt is desired to be greater than tp to ensure proper operation of the prior art DPLA 150.
On the other hand, the DPLA 150 is also desired to operate with ever faster speed with Ø1 and Ø2 having higher frequency. With such higher frequency of Ø1 and Ø2, the delay relationship of Δt>tp is more difficult to maintain since Δt cannot be easily controlled with the higher frequency of Ø1 and Ø2. In addition, tp is difficult to control as the propagation delay through the AND-plane.
As an unfortunate result, with higher frequency of Ø1 and Ø2, the DPLA 150 may not operate properly because of the delay constraint between Ø1 and Ø2. Thus, a DPLA (dynamic programmable logic array) without such a delay constraint between the two clock signals Ø1 and Ø2 of the AND-plane and the OR-plane is desired such that the DPLA may properly operate even at higher frequency.